1. Field of the Invention
The present invention relates to a magnetic memory, which stores data in a magnetoresistive effect element and a manufacturing method thereof.
2. Related Background of the Invention
Recently, as a memory device employed in information processing apparatus such as computer and communication device, there is growing interest in a MRAM (Magnetic Random Access Memory). Since the MRAM stores data by means of magnetism, unlike volatile memory such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), it has not such disadvantage that information is lost due to a power break-off. Also, compared with conventional nonvolatile storage such as flash EEPROM and hard disk device, the MRAM is superior in access speed, reliability, power consumption and so on. Accordingly, the MRAM may perform both of the functions as a volatile memory such as DRAM and SRAM and as a nonvolatile storage such as flash EEPROM and hard disk device. An information apparatus, which is capable of, so called, ubiquitous computing enabling information processing anytime, anywhere, is now progressively under development. The MRAM is expected to perform as a key device in such information apparatus.
FIG. 39A is a side sectional view showing an example of structure of a memory area 100 in a conventional MRAM. The conventional MRAM is equipped with a plurality of wirings 102 extending in one direction and a plurality of wirings 104 extending in the direction crossing the wirings 102. The memory area 100 is formed in every area where the wirings 102 and 104 cross each other. Each memory area 100 has a tunneling magnetoresistive element (referred to as TMR element) 101, which utilizes the tunneling magnetoresistive (TMR) effect. As shown in FIG. 39B, the TMR element 101 includes a first magnetic layer (magneto-sensitive layer) 101a of which magnetizing direction A changes depending on the external magnetic field, a second magnetic layer 101c of which magnetizing direction B is fixed by an antiferromagnetic layer 101d and a nonmagnetic insulating layer 101b sandwiched between the first magnetic layer 101a and the second magnetic layer 101c. By controlling the magnetizing direction A of the first magnetic layer 101a by means of the synthetic magnetic field from the wirings 102 and 104 to be parallel or anti-parallel with the magnetizing direction B, binary data of 0 or 1 are written in the TMR element 101. The resistant value in the thickness direction of the TMR element 101 varies depending on the magnetizing direction A in the first magnetic layer 101a and the magnetizing direction B in the second magnetic layer 101c; i.e., whether the directions are parallel or anti-parallel with each other. Accordingly, to read the binary data from the TMR element 101, the transistor 105 is set to the conductive status to flow the current from the wiring 102 connected to the first magnetic layer 101a to the wiring 103 connected to the second magnetic layer 101c. Based on the current value or the potential difference between the first magnetic layer 101a and the second magnetic layer 101c, it is determined whether which value of the binary data is recorded.
The same configurations as that of the above MRAM are disclosed in, for example, Patent Documents 1 and 2.
There resides the following problem in the configuration of the MRAM shown in FIG. 39A and FIG. 39B. That is, in this MRAM, it is preferred that the magnetizing direction A of the first magnetic layer 101a is inverted only in the TMR element 101 which is given with the magnetic field from both of the wirings 102 and 104. However, the wirings 102 and 104 provide the magnetic field to every TMR element 101 disposed along the respective extending direction. Accordingly, there is a possibility that, in the TMR element 101 other than a target TMR element 101 to be written with binary data, the magnetizing direction A of the first magnetic layer 101a could be erroneously inverted by the magnetic field from the wiring 102 or 104.
As a technique to prevent such erroneous writes, for example, a magnetic memory disclosed in the patent document 3 is known. This magnetic memory is equipped with a TMR element for each memory area (memory cell), a wiring (cell bit line) for flowing the write current to the TMR element and a transistor connected to the cell bit line. Thus, by controlling the write current for writing binary data to the TMR element using the transistor, only the target TMR element to be written with binary data is given with the magnetic field.
[Patent document 1] Japanese Patent Application Laid-open No. 2001-358315
[Patent document 2] Japanese Patent Application Laid-open No. 2002-110938
[Patent document 3] Japanese Patent Application Laid-open No. 2004-153182
However, there resides the following common problem in the configurations disclosed in the patent documents 1 to 3. That is, in these MRAM configurations, the TMR elements are disposed between the wirings (for example, the wirings 102 in FIG. 39A, or bit lines BL in the patent document 3 etc), which extend through pluralities of memory areas and the substrate. In other words, the TMR elements are disposed within the layer (wiring layer) in which a wiring system extending over plural memory areas is formed. On the other hand, on the surface of the substrate on which the wiring layer is built up, a semiconductor element area such as a transistor for controlling the current for reading the binary data from the TMR element (for example, the transistor 105 in FIG. 39A etc) and a transistor for controlling the write current for writing binary data to the TMR element (for example, write select transistor 19 in the patent document 3) is formed. In such MRAM configuration, ferromagnetic material such as Mn, Fe, Ni and Co diffused (migration) from the TMR element into the wiring layer gradually reaches to the transistor on the substrate surface as time passes, mixes with another dopant (contamination), causing a deterioration of the electrical characteristics of the transistor. Accordingly, the life of the MRAM is largely reduced. Also, in the manufacturing process of the MRAM, there is a possibility that ferromagnetic material is mixed into the semiconductor element area formed on the substrate surface.
The present invention has been proposed in view of the above-described problems. An object of the present invention is to provide a manufacturing method of a magnetic memory capable of reducing the diffusion of the ferromagnetic material into semiconductor element area, and a magnetic memory capable of preventing the ferromagnetic material from being mixed into the semiconductor element area in the manufacturing process thereof.